Field
Innovations herein relate generally to increasing the performance of static random access memory (SRAM), and, more specifically, to systems and methods including or involving dual- or multi-pipe multibank SRAMs.
Description of Related Information
By way of illustration, with regard to Quad burst-of-2 (Quad-B2) SRAMs for example, since two operations—a Read and a Write—are initiated per clock cycle, a single-bank SRAM must execute a Read and a Write operation, to any pair of random addresses, together (and sequentially) within a single clock cycle. Additional clock cycles may be used to pipeline Address & Write Data from SRAM input pins to the memory array, and to pipeline Read Data from the memory array to SRAM output pins, but the Read and Write memory accesses themselves must be executed together within a single clock cycle. Here, then, such operations must be executed sequentially, as simultaneous accesses would perforce have to be initiated to different banks. And single bank devices don't have multiple banks.
Further, in single-bank Quad-B2 SRAMs with optimized Read and Write pipelines, the maximum operating frequency (which equates to the maximum performance of the device) is therefore equal to one divided by the minimum amount of time “tRW” required to execute the R/W pair of operations. For example, if tRW=2 ns, then the maximum operating frequency is ½ ns=500 MHz.
Note that such single-bank Quad-B2 SRAMs typically utilize single Read and Write pipelines. In such SRAMs, utilizing multiple pipelines cannot improve the maximum operating frequency of the SRAM beyond that described above. That is, such single-bank Quad-B2 SRAMs are “single-pipe” as well.
As set forth below, one or more aspects of the present inventions may overcome these or other drawbacks and/or otherwise impart innovative features.